Analog-to-digital converters (ADCs) have widespread application. One growing application is in battery operated, portable devices, such as for data conversion in portable video devices. This application requires relatively low power, high throughput and low precision. Illustrative parameters include a minimum of 8 bits of conversion with a throughput of 20 M samples/second. In order to make data conversion an insignificant part of the total system power drawn from the battery, power levels of less than a few milliwatts are desirable.
One conventional low power ADC architecture utilizes a plurality of pipelined, or series-coupled stages, with each stage converting one bit of data. Each stage includes a sample and hold circuit, an analog-to-digital converter, a digital-to-analog converter, a summing circuit and an amplifying circuit. The sample and hold circuit shift registers the analog sample and the analog-to-digital converter provides the output bit for the stage. The value of the output bit is converted back into an analog signal by the digital-to-analog converter and is subtracted from the input analog sample by the summing circuit. The difference signal is then scaled by the amplifying circuit and applied to a subsequent stage for conversion of the next most significant bit.
In order to limit noise, such as thermal noise, shot noise and flicker noise, to an acceptable level, the capacitance value used in circuit components must be greater than a predetermined minimum. As one example, where the thermal noise is limited to one-half of the least significant bit, the minimum capacitance can be found by: ##EQU1##
where V.sub.R is the input voltage range, P is the precision, k is Boltzmann's constant, T is the temperature, and C is the resulting minimum capacitance. This minimum capacitance dictates the current that the operational amplifiers must drive to achieve a given throughput which, in turn, dictates the power dissipated by the operational amplifiers. As a result, power dissipation for an illustrative 12 bit, 20 M samples/second ADC can be on the order of one-half watt.
Various techniques have been proposed to reduce the power dissipation associated with pipelined ADCs. These include the scaling of the sampling capacitance in each of the pipelined stages and resolution of more bits per stage which reduces the thermal noise capacitance requirements in later stages, both of which are described by D. W. Cline, et al. in "A Power Optimized 13-b, 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 .mu.m CMOS," IEEE Journal of Sold-State Circuits, vol. 31, no. 3, pp. 294-303, 1996. Another technique, which was proposed by P. C. Yu et al. in "A 2.5-V, 12-b, 5Msample/s Pipelined CMOS ADC," IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, 1996, is time multiplexing one operational amplifier to serve both the sampling and amplifying functions, which saves DC power.